Hardware Architecture of Low-Power ALU using Clock Gating

With the scaling of technology, need for high performance and more functionality, power dissipation becomes a major bottle neck for microprocessor systems design, because clock power can be significant in high performance systems. We propose a low power ALU for high performance systems, which make use of clock gating to reduce clock power. This low-power ALU based on the observation that while one functional unit is working other functional units remain ideal, but they are connected to clock and dissipating significant amount of power. By using clock gating technique we achieved significant amount of power saving at high frequency operations. Functionality of proposed ALU is tested using Xilinx 12.1i software tool. Power analysis of ALU done by using Xilinx’s xpower power analysis tool. It is observed that designed ALU dissipating power of 24 mw when it is operated at the clock frequency of 15 MHz and supply voltage of 2.4V under load current of 16 mA. ALU is successfully implemented on Xilinx Spatran 3E FPGA.